   
################################################################################
##$Date: 2008/05/30 00:57:53 $
##$RCSfile: run_isim_pl.ejava,v $
##$Revision: 1.1.2.1 $
################################################################################
##   ____  ____ 
##  /   /\/   / 
## /___/  \  /    Vendor: Xilinx 
## \   \   \/     Version : 1.5
##  \   \         Application : RocketIO GTX Wizard 
##  /   /         Filename : run_isim.pl
## /___/   /\     Timestamp : 11/12/2007 09:12:43
## \   \  /  \ 
##  \___\/\___\ 
##
##
## Script RUN_ISIM.PL
## Generated by Xilinx RocketIO GTX Wizard


##***************************** Beginning of Script ***************************
    
    
$top_module = "EXAMPLE_TB";
$exe_file = "$top_module.exe";
$XILINX = $ENV{XILINX};


##MGT Wrapper
push @Filelist, "../src/rocketio_gtx_tile.v";
push @Filelist, "../src/rocketio_gtx.v";

push @Filelist, "../src/mgt_usrclk_source_pll.v";

##Example Design modules
push @Filelist, "../example/frame_gen.v";
push @Filelist, "../example/frame_check.v";
push @Filelist, "../example/example_mgt_top.v";


##Other modules
push @Filelist, "$XILINX/verilog/src/glbl.v";

##Testbench file
push @Filelist, "../testbench/example_tb.v";


#Generate PRJ file
open (PRJ_FILE, ">sim_isim.prj");
foreach $module(@Filelist)
{
print PRJ_FILE "verilog work ". $module . "\n";
}
close (PRJ_FILE);


#Compile and link source files
system("fuse -prj sim_isim.prj -lib unisims_ver=$XILINX/verilog/hdp/lin/unisims_ver -top $top_module -top glbl -o $exe_file");

##--Generate waveform trace--##
system("./$exe_file -tclbatch isim_wave.tcl -wavefile isim_wave");


##--View simulation wave--##
system("isimwave isim_wave.xwv");

